The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 31, 2016

Filed:

Aug. 11, 2015
Applicant:

Texas Instruments Incorporated, Dallas, TX (US);

Inventor:

Rajeev Dinkar Joshi, Cupertino, CA (US);

Assignee:
Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
H01L 23/495 (2006.01); H01L 25/16 (2006.01); H01L 25/00 (2006.01); H02M 7/00 (2006.01); H01L 23/498 (2006.01); H01L 23/31 (2006.01);
U.S. Cl.
CPC ...
H01L 23/49575 (2013.01); H01L 23/3114 (2013.01); H01L 23/49503 (2013.01); H01L 23/49531 (2013.01); H01L 23/49548 (2013.01); H01L 23/49562 (2013.01); H01L 23/49568 (2013.01); H01L 23/49861 (2013.01); H01L 25/165 (2013.01); H01L 25/50 (2013.01); H02M 7/003 (2013.01); H01L 23/3107 (2013.01); H01L 23/49838 (2013.01);
Abstract

Power supply system comprises vertically sequentially a QFN leadframe, a first chip with FET terminals on opposite sides, a flat interposer, and a second chip with FET terminals and the terminals of the integrated driver-and-control circuit on a single side. Leadframe pad has a portion recessed as pocket with a depth and an outline suitable for attaching the first chip with one terminal in the pocket and the opposite terminal co-planar with the un-recessed pad surface. The interposer comprises metal patterned in traces separated by gaps; the traces include metal of a first height and metal of a second height smaller than the first height, and insulating material filling the gaps and the height differences; one interposer side attached to the leadframe pad with the first chip, the opposite interposer side attached to the terminals of the second chip.


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