The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 31, 2016

Filed:

Mar. 28, 2013
Applicants:

Thorbjorn Ebefors, Huddinge, SE;

Daniel Perttu, Hasselby, SE;

Inventors:

Thorbjorn Ebefors, Huddinge, SE;

Daniel Perttu, Hasselby, SE;

Assignee:

SILEX MICROSYSTEMS AB, Jarfalla, SE;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/768 (2006.01); H01L 23/14 (2006.01); H01L 21/288 (2006.01); H01L 23/522 (2006.01); H01L 23/48 (2006.01); H01L 23/498 (2006.01);
U.S. Cl.
CPC ...
H01L 21/76831 (2013.01); H01L 21/2885 (2013.01); H01L 21/7684 (2013.01); H01L 21/76807 (2013.01); H01L 21/76871 (2013.01); H01L 21/76879 (2013.01); H01L 21/76898 (2013.01); H01L 23/147 (2013.01); H01L 23/481 (2013.01); H01L 23/49827 (2013.01); H01L 23/5226 (2013.01); H01L 23/49811 (2013.01); H01L 2924/0002 (2013.01);
Abstract

A method of providing a via hole and routing structure includes: providing a substrate wafer having recesses and blind holes provided in the surface of the wafer; providing an insulating layer in the recesses and holes; metallizing the holes and recesses; and removing the oxide layer in the bottom of the holes to provide contact between the back side and the front side of the wafer. A semiconductor device, including a substrate having at least one metallized via extending through the substrate and at least one metallized recess forming a routing together with the via. There is an oxide layer on the front side field and on the back side field. The metal in the recess and the via is flush with the oxide on the field on at least the front side, whereby a flat front side is provided. The thickness of the semiconductor device is <300 μm.


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