Data recovery in a 3d memory device with a short circuit between word lines

Abstract

Techniques for detecting word line layers which are shorted together due to a defect in a three-dimensional stack memory device, and for recovering data. The memory device comprises blocks of memory cells in which each block has a separate stack of word line layers but the word line layers at a common height in the different stacks are connected. A process to detect a short circuit occurs when an nth word line layer (WLn) in an ith block fails to successfully complete programming. A determination is made as to whether WLn is shorted to WLn−1 and/or WLn+1. If WLn is shorted to WLn+1 but not WLn−1 in the ith block, a recovery read process is performed to read the data which has been programmed into the memory cells of WLn of the previously-programmed blocks. The recovery read process uses upshifted control gate read voltages due to the short circuit.