The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 31, 2016

Filed:

Jan. 23, 2014
Applicant:

Nvidia Corporation, Santa Clara, CA (US);

Inventors:

Haiyan Gong, Santa Clara, CA (US);

Lei Wang, Santa Clara, CA (US);

Sing-Rong Li, Santa Clara, CA (US);

Hwong-Kwo Lin, Santa Clara, CA (US);

Pai-Yi Chang, Santa Clara, CA (US);

Assignee:

NVIDIA CORPORATION, Santa Clara, CA (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G11C 11/412 (2006.01); G11C 11/419 (2006.01); G11C 5/14 (2006.01);
U.S. Cl.
CPC ...
G11C 11/419 (2013.01); G11C 5/147 (2013.01);
Abstract

A hybrid write-assist memory system includes an array voltage supply and a static random access memory (SRAM) cell that is controlled by bit lines and a word line and employs a separable cell supply voltage coupled to the array voltage supply. Additionally, the hybrid write-assist memory system includes a supply voltage droop unit that is coupled to the SRAM cell and provides a voltage reduction of the separable cell supply voltage during a write operation. Also, the hybrid write-assist memory system includes a negative bit line unit that is coupled to the supply voltage droop unit and provides a negative bit line voltage concurrently with the voltage reduction of the separable cell supply voltage during the write operation. A method of operating a hybrid write-assist memory system is also provided.


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