The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 31, 2016

Filed:

Jul. 08, 2014
Applicant:

Taiwan Semiconductor Manufacturing Company, Ltd., Hsin-Chu, TW;

Inventors:

Harry Hak-Lay Chuang, Singapore, SG;

Cheng-Cheng Kuo, Hsinchu, TW;

Ching-Che Tsai, Zhubei, TW;

Bao-Ru Young, Zhubei, TW;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/027 (2006.01); G06F 17/50 (2006.01); H01L 21/8234 (2006.01); H01L 21/28 (2006.01); H01L 21/3213 (2006.01); H01L 29/66 (2006.01); H01L 27/02 (2006.01); H01L 21/8238 (2006.01); G03F 1/00 (2012.01); H01L 29/49 (2006.01); H01L 29/51 (2006.01);
U.S. Cl.
CPC ...
G06F 17/5081 (2013.01); G03F 1/00 (2013.01); G06F 17/5045 (2013.01); H01L 21/0274 (2013.01); H01L 21/28123 (2013.01); H01L 21/32139 (2013.01); H01L 21/823456 (2013.01); H01L 21/823842 (2013.01); H01L 27/0207 (2013.01); H01L 29/66545 (2013.01); H01L 29/4966 (2013.01); H01L 29/513 (2013.01); H01L 29/517 (2013.01);
Abstract

The present disclosure provides a method of fabricating a semiconductor device. A first layout design for a semiconductor device is received. The first layout design includes a plurality of gate lines and an active region that overlaps with the gate lines. The active region includes at least one angular corner that is disposed adjacent to at least one of the gate lines. The first layout design for the semiconductor device is revised via an optical proximity correction (OPC) process, thereby generating a second layout design that includes a revised active region with a revised corner that protrudes outward. Thereafter, the semiconductor device is fabricated based on the second layout design.


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