The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
May. 24, 2016
Filed:
Dec. 27, 2012
Taiwan Semiconductor Manufacturing Co., Ltd., Hsin-Chu, TW;
Tsung-Hsiung Lee, New Taipei, TW;
Shi-Hung Wang, Houli Township, TW;
Kuang-Kai Yen, Kaohsiung, TW;
Wei-Li Chen, Hsinchu, TW;
Yung-Hsu Chuang, Hsinchu, TW;
Shih-Hung Lan, Jhubei, TW;
Fan-ming Kuo, Zhubei, TW;
Chewn-Pu Jou, Hsinchu, TW;
Fu-Lung Hsueh, Kaohsiung, TW;
Taiwan Semiconductor Manufacturing Co., Ltd., Hsin-Chu, TW;
Abstract
The present disclosure relates to a device and method to reduce the dynamic/static power consumption of an MCML logic device. In order to retain register contents during power off mode, an MCML retention latch and flip-flop are disclosed. Retention Latch circuits in MCML architecture are used to retain critical register contents during power off mode, wherein combination logic including clock buffers on the clock tree paths are powered off to reduce dynamic/static power consumption. The MCML retention flip-flop comprises a master latch and a slave latch, wherein a power switch is added to the master latch to power the master latch off during power off mode. The slave latch includes pull-down circuits that remain active to enable the slave latch to retain data at a proper voltage level during power off mode. Other devices and methods are also disclosed.