The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 24, 2016

Filed:

May. 27, 2013
Applicant:

United Microelectronics Corp., Hsin-Chu, TW;

Inventors:

Chieh-Te Chen, Kaohsiung, TW;

Feng-Yi Chang, Tainan, TW;

Hsuan-Hsu Chen, Tainan, TW;

Assignee:

UNITED MICROELECTRONICS CORP., Science-Based Industrial Park, Hsin-Chu, TW;

Attorneys:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 29/417 (2006.01); H01L 29/06 (2006.01); H01L 21/311 (2006.01); H01L 21/768 (2006.01); H01L 23/485 (2006.01); H01L 29/66 (2006.01);
U.S. Cl.
CPC ...
H01L 29/41775 (2013.01); H01L 21/31144 (2013.01); H01L 21/76816 (2013.01); H01L 21/76897 (2013.01); H01L 23/485 (2013.01); H01L 29/0692 (2013.01); H01L 29/66545 (2013.01); H01L 2924/0002 (2013.01);
Abstract

A semiconductor device with a self-aligned contact and a method of manufacturing the same, wherein the method comprises the step of forming a 1st dielectric layer on gate structures, form a self-aligned contact trench between two gate structures, forming an 2nd dielectric layer on the 1st dielectric layer and in the self-aligned contact trench; patterning the 2nd dielectric layer into a 1st portion on the 1st dielectric layer and a 2nd portion filling in the self-aligned contact trench, using the 2nd dielectric layer as a mask to etch the 1st dielectric layer, and forming a metal layer and a self-aligned contact simultaneously in the 1st dielectric layer and in the self-aligned contact trench.


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