The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 24, 2016

Filed:

Jul. 20, 2015
Applicant:

Renesas Electronics Corporation, Kawasaki-shi, Kanagawa, JP;

Inventors:

Nobuto Nakanishi, Ibaraki, JP;

Yoshiyuki Kawashima, Kanagawa, JP;

Akio Nishida, Kanagawa, JP;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/28 (2006.01); H01L 27/115 (2006.01); H01L 21/265 (2006.01); H01L 21/3105 (2006.01); H01L 29/66 (2006.01); H01L 29/51 (2006.01); H01L 21/3213 (2006.01); H01L 29/45 (2006.01); H01L 29/423 (2006.01);
U.S. Cl.
CPC ...
H01L 27/11568 (2013.01); H01L 21/26513 (2013.01); H01L 21/28282 (2013.01); H01L 21/31053 (2013.01); H01L 21/32133 (2013.01); H01L 27/11563 (2013.01); H01L 29/42344 (2013.01); H01L 29/456 (2013.01); H01L 29/513 (2013.01); H01L 29/66545 (2013.01);
Abstract

To provide a semiconductor device having improved reliability. A semiconductor device is provided forming a control gate electrode for memory cell on a semiconductor substrate via a first insulating film; forming a memory gate electrode for memory cell, which is adjacent to the control gate electrode, on the semiconductor substrate via a second insulating film having a charge storage portion; forming ntype semiconductor regions for source or drain in the semiconductor substrate by ion implantation; forming sidewall spacers on the side wall of the control gate electrode and the memory gate electrode; forming ntype semiconductor regions for source or drain in the semiconductor substrate by ion implantation; and removing an upper portion of the second insulating film present between the control gate electrode and the memory gate electrode. A removal length of the second insulating film is larger than the depth of the ntype semiconductor regions.


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