The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 24, 2016

Filed:

Jun. 03, 2015
Applicant:

Huawei Technologies Co., Ltd., Shenzhen, CN;

Inventors:

Huili Fu, Shenzhen, CN;

Xiaodong Zhang, Shanghai, CN;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 23/52 (2006.01); H01L 25/065 (2006.01); H01L 23/48 (2006.01); H01L 23/528 (2006.01); H01L 23/538 (2006.01); H01L 23/498 (2006.01);
U.S. Cl.
CPC ...
H01L 25/0652 (2013.01); H01L 23/481 (2013.01); H01L 23/528 (2013.01); H01L 23/5384 (2013.01); H01L 23/5389 (2013.01); H01L 23/49816 (2013.01); H01L 2224/16225 (2013.01); H01L 2225/06548 (2013.01); H01L 2225/06555 (2013.01); H01L 2225/06572 (2013.01);
Abstract

A chip stacked package structure includes a first chip and a second chip, where the second chip is stacked with the first chip and the second chip includes a package layer and a first routing layer, where the package layer includes at least two dies and an attaching part configured to attach the at least two dies, where the attaching part is provided with multiple vias, with a part of vias in the multiple vias disposed at an outer periphery of the at least two dies, and the other part of vias in the multiple vias disposed between the at least two dies, and the first routing layer electrically connects the at least two dies; where the package layer is located between the first routing layer and the first chip, an electrically conductive material is provided in the multiple vias.


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