The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 24, 2016

Filed:

Aug. 05, 2014
Applicants:

Viswanathan Lakshminarayan, Phoenix, AZ (US);

Michael E. Watts, Scottsdale, AZ (US);

David F. Abdo, Scottsdale, AZ (US);

Inventors:

Viswanathan Lakshminarayan, Phoenix, AZ (US);

Michael E. Watts, Scottsdale, AZ (US);

David F. Abdo, Scottsdale, AZ (US);

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 29/84 (2006.01); H01L 23/552 (2006.01); H01L 23/053 (2006.01); H01L 21/52 (2006.01);
U.S. Cl.
CPC ...
H01L 23/552 (2013.01); H01L 21/52 (2013.01); H01L 23/053 (2013.01);
Abstract

A system and method for packaging a semiconductor device that includes a structure to reduce electromagnetic coupling are presented. The semiconductor device is formed on a substrate. A cover is affixed to the substrate so as to extend over the semiconductor device. An isolation structure of electrically conductive material is coupled to the cover in between components of the semiconductor device, with the isolation structure being configured to reduce inductive coupling between those components during an operation of the semiconductor device. In one version, the isolation structure includes a first leg extending from a ground connection along a side wall of the cover to a cross member contiguous with a primary cover wall that extends over the semiconductor device between the components to be isolated electromagnetically.


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