The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 24, 2016

Filed:

Apr. 17, 2014
Applicant:

Sts Semiconductor & Telecommunications Co., Ltd., Cheonan-si, Chungcheongnam-do, KR;

Inventors:

Jae Bok Yoo, Jeonju-si, KR;

Hyun Hak Jung, Cheonan-si, KR;

Kyoung Min Song, Cheonan-si, KR;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 23/31 (2006.01); H01L 21/56 (2006.01); H01L 23/498 (2006.01); H01L 23/00 (2006.01); H01L 25/10 (2006.01);
U.S. Cl.
CPC ...
H01L 23/3128 (2013.01); H01L 21/56 (2013.01); H01L 23/49811 (2013.01); H01L 23/49816 (2013.01); H01L 24/16 (2013.01); H01L 24/48 (2013.01); H01L 25/105 (2013.01); H01L 2224/16225 (2013.01); H01L 2224/48227 (2013.01); H01L 2225/1023 (2013.01); H01L 2924/12042 (2013.01); H01L 2924/1533 (2013.01); H01L 2924/15311 (2013.01); H01L 2924/1815 (2013.01);
Abstract

A method of manufacturing a stacked package includes a first process of stacking a semiconductor chip on an upper surface of a PCB having a wiring pattern and a via-hole pad, a second process of forming a photoresist (PR) layer on the upper surface of the PCB having the semiconductor chip and the via-hole pad, a third process of removing the photoresist layer of a remaining region except for an upper portion of the via-hole pad so that a photoresist layer of a via-hole region remains only at the upper portion of the via-hole pad, a fourth process of forming a molding layer by molding the upper surface of the PCB having the semiconductor chip to expose an upper surface of the photoresist layer of the via-hole region, and a fifth process of removing the photoresist layer of the via-hole region to form a via-hole on the via-hole pad.


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