The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 24, 2016

Filed:

Aug. 28, 2012
Applicants:

Prakash Krishnamoorthy, Bethlehem, PA (US);

Ramesh C. Tekumalla, Breinisgsville, PA (US);

Parag Madhani, Allentown, PA (US);

Inventors:

Prakash Krishnamoorthy, Bethlehem, PA (US);

Ramesh C. Tekumalla, Breinisgsville, PA (US);

Parag Madhani, Allentown, PA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 9/30 (2006.01); G06F 9/32 (2006.01); G06F 9/34 (2006.01); G06F 9/38 (2006.01);
U.S. Cl.
CPC ...
G06F 9/30181 (2013.01); G06F 9/30156 (2013.01); G06F 9/32 (2013.01); G06F 9/322 (2013.01); G06F 9/34 (2013.01); G06F 9/3806 (2013.01);
Abstract

Coding circuitry comprises at least an encoder configured to encode an instruction address for transmission to a decoder. The encoder is operative to identify the instruction address as belonging to a particular one of a plurality of groups of instruction addresses associated with respective distinct program constructs, and to encode the instruction address based on the identified group. The decoder is operative to identify the encoded instruction address as belonging to the particular one of a plurality of groups of instruction addresses associated with respective distinct program constructs, and to decode the encoded instruction address based on the identified group. The coding circuitry may be implemented as part of an integrated circuit or other processing device that includes associated processor and memory elements. In such an arrangement, the processor may generate the instruction address for delivery over a bus to the memory.


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