The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
May. 17, 2016
Filed:
Dec. 22, 2011
Nicholas P. Cowley, Wroughton, GB;
Andrew D. Talbot, Chieveley, GB;
Isaac Ali, Mississauga, CA;
Keith Pinson, Swindon, GB;
Colin L. Perry, Swindon, GB;
Matthew T. Aitken, Swindon, GB;
Chi Man Kan, Swindon, GB;
Mark S. Mudd, Wootton Bassett, GB;
Stephen J. Spinks, Swindon, GB;
Alan J. Martin, Plymouth, GB;
William L. Barber, Bampton, GB;
Nicholas P. Cowley, Wroughton, GB;
Andrew D. Talbot, Chieveley, GB;
Isaac Ali, Mississauga, CA;
Keith Pinson, Swindon, GB;
Colin L. Perry, Swindon, GB;
Matthew T. Aitken, Swindon, GB;
Chi Man Kan, Swindon, GB;
Mark S. Mudd, Wootton Bassett, GB;
Stephen J. Spinks, Swindon, GB;
Alan J. Martin, Plymouth, GB;
William L. Barber, Bampton, GB;
Intel Corporation, Santa Clara, CA (US);
Abstract
A dual mode voltage regulator according to one embodiment includes a passive regulator circuit; a switching regulator circuit; and a controller circuit configured to monitor operational parameters of the dual mode voltage regulator and selectively couple either the passive regulator circuit or the switching regulator circuit between an input voltage port and an output load. The selective coupling is based on the monitoring of parameters including current through the output load, voltage at the input voltage port and voltage at the output load as well as the availability of a system clock signal.