The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 17, 2016

Filed:

Dec. 17, 2014
Applicant:

Globalfoundries Singapore Pte. Ltd., Singapore, SG;

Inventors:

Shyue Seng Tan, Singapore, SG;

Eng Huat Toh, Singapore, SG;

Elgin Quek, Singapore, SG;

Yanzhe Tang, Singapore, SG;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/28 (2006.01); H01L 27/115 (2006.01); H01L 29/423 (2006.01); H01L 29/788 (2006.01); G11C 16/04 (2006.01); H01L 29/66 (2006.01);
U.S. Cl.
CPC ...
H01L 27/11568 (2013.01); G11C 16/04 (2013.01); G11C 16/0475 (2013.01); H01L 21/28273 (2013.01); H01L 21/28282 (2013.01); H01L 27/11521 (2013.01); H01L 27/11526 (2013.01); H01L 27/11573 (2013.01); H01L 29/42324 (2013.01); H01L 29/42328 (2013.01); H01L 29/42344 (2013.01); H01L 29/66825 (2013.01); H01L 29/7883 (2013.01);
Abstract

A device having a substrate prepared with a memory cell region having a memory cell is disclosed. The memory cell includes an access transistor and a storage transistor. The access transistor includes first and second source/drain (S/D) regions and the storage transistor includes first and second storage S/D regions. The access and storage transistors are coupled in series and the second S/D regions being a common S/D region. An erase gate is disposed over the common S/D region. A program gate is disposed over the first storage S/D region. Such an arrangement of the memory cell decouples a program channel and an erase channel.


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