The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
May. 17, 2016
Filed:
Feb. 11, 2015
Applicant:
Sandisk Technologies Inc., Plano, TX (US);
Inventors:
Deepanshu Dutta, Fremont, CA (US);
Shih-Chung Lee, Yokohama, JP;
Assignee:
SanDisk Technologies Inc., Plano, TX (US);
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 11/34 (2006.01); G11C 16/14 (2006.01); G11C 16/04 (2006.01); G11C 16/34 (2006.01); G11C 16/26 (2006.01);
U.S. Cl.
CPC ...
G11C 16/14 (2013.01); G11C 16/0483 (2013.01); G11C 16/26 (2013.01); G11C 16/3445 (2013.01);
Abstract
Reducing peak current and/or power consumption during erase verify of a non-volatile memory is disclosed. During an erase verify, memory cells are verified at a strict reference level that is deeper (e.g., lower threshold voltage) than a target reference level. After the strict erase verify, strings of memory cells that pass the strict erase verify are locked out from a next erase verify at the target reference level. Locked out strings do not conduct a significant current during erase verify, thus reducing peak current and/or power consumption.