The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 10, 2016

Filed:

Sep. 24, 2014
Applicant:

Macronix International Co., Ltd., Hsinchu, TW;

Inventors:

Pei-Ci Jhang, Hsinchu, TW;

Chun-Min Cheng, Hsinchu, TW;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 27/115 (2006.01); H01L 21/28 (2006.01); H01L 29/423 (2006.01);
U.S. Cl.
CPC ...
H01L 27/11568 (2013.01); H01L 21/28282 (2013.01); H01L 29/42356 (2013.01);
Abstract

A method of manufacturing a semiconductor device is provided. Gate structures are formed on a substrate, and a first dielectric layer having grooves is formed between two adjacent gate structures. An upper surface of the first dielectric layer is lower than an upper surface of the gate structures. Afterwards, an intermediate layer is formed to cover the gate structures, the first dielectric layer, and the grooves, and openings are formed therein. Each opening is formed between two adjacent gate structures, and the first dielectric layer is removed through the opening. Next, a second dielectric layer is formed on the intermediate layer, so as to define an air gap between two adjacent gate structures. Furthermore, a semiconductor device is provided.


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Jhang, Pei-Ci. (2016). Semiconductor memory array with air gaps between adjacent gate structures and method of manufacturing the same (U.S. Patent No. 9337208). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/9337208

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