The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 10, 2016

Filed:

Nov. 25, 2013
Applicants:

Jiyoung Kim, Yongin-si, KR;

Sungho Jang, Seoul, KR;

Kang-uk Kim, Seoul, KR;

Kyung-eun Kim, Seoul, KR;

Daeik Kim, Hwaseong-si, KR;

Hyoungsub Kim, Seongnam-si, KR;

Nakjin Son, Suwon-si, KR;

Dong Jin Lee, Seoul, KR;

Yoosang Hwang, Suwon-si, KR;

Jihye Hwang, Boryeong-si, KR;

Inventors:

Jiyoung Kim, Yongin-si, KR;

Sungho Jang, Seoul, KR;

Kang-Uk Kim, Seoul, KR;

Kyung-Eun Kim, Seoul, KR;

Daeik Kim, Hwaseong-si, KR;

Hyoungsub Kim, Seongnam-si, KR;

Nakjin Son, Suwon-si, KR;

Dong Jin Lee, Seoul, KR;

Yoosang Hwang, Suwon-si, KR;

Jihye Hwang, Boryeong-si, KR;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 27/108 (2006.01); H01L 27/088 (2006.01);
U.S. Cl.
CPC ...
H01L 27/10826 (2013.01); H01L 27/0886 (2013.01); H01L 27/10894 (2013.01);
Abstract

A semiconductor device may include a substrate having a first region and a second region on a surface thereof, and a first semiconductor fin on the first region of the substrate with the first semiconductor fin including a first trench therethrough. A first gate electrode may be provided in the first trench, and first and second source/drain regions may be provided in the first semiconductor fin, with the first gate electrode between the first and second source/drain regions. A second semiconductor fin may be provided on the second region of the substrate with the second semiconductor fin including a second trench therethrough, a second gate electrode may be provided in the second trench, and third and fourth source/drain regions may be provided in the second semiconductor fin with the second gate electrode being between the third and fourth source/drain regions.


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