The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 10, 2016

Filed:

Mar. 14, 2013
Applicants:

Zhongying Zhang, Portland, OR (US);

Erik G. Hallnor, Beaverton, OR (US);

Stanley S. Kulick, Portland, OR (US);

Jeffrey L. Miller, Vancouver, WA (US);

Inventors:

Zhongying Zhang, Portland, OR (US);

Erik G. Hallnor, Beaverton, OR (US);

Stanley S. Kulick, Portland, OR (US);

Jeffrey L. Miller, Vancouver, WA (US);

Assignee:

Intel Corporation, Santa Clara, CA (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G06F 12/08 (2006.01);
U.S. Cl.
CPC ...
G06F 12/0891 (2013.01); G06F 12/0804 (2013.01); G06F 12/0815 (2013.01); G06F 12/0826 (2013.01); G06F 12/0864 (2013.01); G06F 12/0895 (2013.01); G06F 2212/60 (2013.01);
Abstract

A processing device and method for cache control including tracking updates to the line state of a cache superline are described. In response to a request pertaining to a superline, a cache controller of the processing device can perform one or more read-modify-write (RMW) operations to (a) a line state vector of a line state array and (b) a counter of the line state array. Based on a determination that one or more requests to the superline have completed, the line state vector from the line state array can be written to a tag array. The cache controller can track pending line state updates to a superline outside of the tag array, and a line state update can occur in the cache controller, rather than awaiting completion of all outstanding operations on a superline. Updates to multiple line states can be maintained simultaneously, and up-to-date ECCs computed.


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