The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 9336036 B1

PDF
Full Text
Expired
Date of Patent:
May. 10, 2016

Filed:

Mar. 31, 2011
Applicants:

Yaozu Dong, Shanghai, CN;

Yun Wang, Shanghai, CN;

Yunhong Jiang, San Jose, CA (US);

Inventors:

Yaozu Dong, Shanghai, CN;

Yun Wang, Shanghai, CN;

Yunhong Jiang, San Jose, CA (US);

Assignee:

Intel Corporation, Santa Clara, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 9/00 (2006.01); G06F 9/455 (2006.01); G06F 11/14 (2006.01); G06F 11/16 (2006.01); G06F 12/10 (2016.01); G06F 11/20 (2006.01);
U.S. Cl.
CPC ...
G06F 9/45558 (2013.01); G06F 11/1484 (2013.01); G06F 11/1666 (2013.01); G06F 12/1009 (2013.01); G06F 12/1027 (2013.01); G06F 11/20 (2013.01); G06F 2009/45562 (2013.01);
Abstract

A virtualization based system comprises a host and a plurality of virtual machines that may each comprises a guest memory. A virtual machine monitor has access to underlying platform hardware in the system and may control physical resources in the platform. The platform hardware comprises a processor and a memory coupled to the processor. Further, the VMM may manage guest software including guest operating systems running on the virtual machines. A binary translation logic may replace guest memory writing instructions corresponding to a hot spot in guest application with translated codes to generate a mirrored content for the guest memory. The binary translation logic may combine one or more of the guest memory writing instructions in a region and keep the region atomic. The processor may execute the translated codes in an atomic region together to write a content in the guest memory and a mirrored content in a mirroring memory. The VMM may allocate a memory region in the host memory for the mirroring memory. The guest memory comprises one or more guest memory pages and the mirroring memory may comprise one or more mirroring memory pages. The VMM may add an offset to a virtual address of a guest memory page to obtain a virtual address of a mirroring memory page. The VMM may manage or emulate a guest page table comprising a mapping between virtual address to guest physical addresses for the guest memory. The VMM may synchronize a shadow page table with the mapping in the guest page table. The shadow page table comprises a mapping of virtual addresses to host physical addresses for the guest memory and a mapping of virtual addresses to host physical addresses for the mirroring page. Upon a memory failure in the guest memory page, the VMM may restore the content of the corrupted guest memory page from the mirroring memory page.


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