The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
May. 10, 2016
Filed:
May. 28, 2013
Applicant:
Intel Corporation, Santa Clara, CA (US);
Inventors:
James S. Burns, Cupertino, CA (US);
Ashish V. Choubal, Austin, TX (US);
Arvind Raman, Austin, TX (US);
Johan G. Van De Groenendaal, Portland, OR (US);
Assignee:
Intel Corporation, Santa Clara, CA (US);
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 1/32 (2006.01); G06F 1/00 (2006.01); G06F 1/26 (2006.01); G01R 27/00 (2006.01); G06F 1/20 (2006.01);
U.S. Cl.
CPC ...
G06F 1/324 (2013.01); G06F 1/26 (2013.01); G06F 1/3203 (2013.01); G06F 1/3206 (2013.01); G06F 1/3234 (2013.01); G06F 1/206 (2013.01); G06F 1/329 (2013.01);
Abstract
A method and system for dynamic or run-time reallocation of leakage current and dynamic power supply current of a processor. In one embodiment of the invention, the processor uses the variation in the leakage current of the processor to reduce the maximum current dissipation or power supply current of the processor (ICC). By reducing the maximum current dissipation, the system cost can be reduced as a less expensive power delivery system is required in one embodiment of the invention.