The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 03, 2016

Filed:

Feb. 10, 2015
Applicant:

Intermolecular Inc., San Jose, CA (US);

Inventors:

Tony P. Chiang, Campbell, CA (US);

Dipankar Pramanik, Saratoga, CA (US);

Milind Weling, Pleasanton, CA (US);

Assignee:

Intermolecular, Inc., San Jose, CA (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 27/24 (2006.01); H01L 45/00 (2006.01); G11C 13/00 (2006.01);
U.S. Cl.
CPC ...
H01L 45/1253 (2013.01); G11C 13/0002 (2013.01); G11C 13/0007 (2013.01); H01L 27/2409 (2013.01); H01L 27/2463 (2013.01); H01L 45/08 (2013.01); H01L 45/12 (2013.01); H01L 45/1233 (2013.01); H01L 45/14 (2013.01); H01L 45/145 (2013.01); H01L 45/146 (2013.01); G11C 2213/15 (2013.01); G11C 2213/33 (2013.01); G11C 2213/34 (2013.01); G11C 2213/52 (2013.01);
Abstract

A nonvolatile resistive memory element includes an oxygen-gettering layer. The oxygen-gettering layer is formed as part of an electrode stack, and is more thermodynamically favorable in gettering oxygen than other layers of the electrode stack. The Gibbs free energy of formation (ΔfG°) of an oxide of the oxygen-gettering layer is less (i.e., more negative) than the Gibbs free energy of formation of an oxide of the adjacent layers of the electrode stack. The oxygen-gettering layer reacts with oxygen present in the adjacent layers of the electrode stack, thereby preventing this oxygen from diffusing into nearby silicon layers to undesirably increase an SiOinterfacial layer thickness in the memory element and may alternately be selected to decrease such thickness during subsequent processing.


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