The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 03, 2016

Filed:

Feb. 06, 2015
Applicant:

Globalfoundries Inc., Grand Cayman, KY (US);

Inventors:

Ashish Kumar Jha, Saratoga Springs, NY (US);

Yan Ping Shen, Saratoga Springs, NY (US);

Wei Hua Tong, Mechanicville, NY (US);

Haiting Wang, Clifton Park, NY (US);

Min-Hwa Chi, Malta, NY (US);

Assignee:

GLOBALFOUNDRIES Inc., Grand Cayman, KY;

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/336 (2006.01); H01L 21/8234 (2006.01); H01L 29/417 (2006.01); H01L 29/66 (2006.01); H01L 21/311 (2006.01); H01L 21/306 (2006.01); H01L 21/02 (2006.01); H01L 29/04 (2006.01); H01L 29/08 (2006.01); H01L 29/78 (2006.01);
U.S. Cl.
CPC ...
H01L 29/41783 (2013.01); H01L 21/02233 (2013.01); H01L 21/30604 (2013.01); H01L 21/31111 (2013.01); H01L 29/045 (2013.01); H01L 29/0847 (2013.01); H01L 29/6653 (2013.01); H01L 29/66568 (2013.01); H01L 29/78 (2013.01);
Abstract

Methods of fabricating transistors having raised active region(s) with at least partially angled upper surfaces are provided. The method includes, for instance: providing a gate structure disposed over a substrate, the gate structure including a conformal spacer layer; forming a raised active region adjoining a sidewall of the conformal spacer layer; providing a protective material over the raised active region; selectively etching-back the sidewall of the conformal spacer layer, exposing a side portion of the raised active region below the protective material; and etching the exposed side portion of the raised active region to partially undercut the protective material, wherein the etching facilitates defining, at least in part, an at least partially angled upper surface of the raised active region of the transistor.


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