The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
May. 03, 2016
Filed:
Oct. 17, 2014
Applicant:
Sandisk Technologies Inc., Plano, TX (US);
Inventors:
Johann Alsmeier, San Jose, CA (US);
Raghuveer S. Makala, Sunnyvale, CA (US);
Xiying Costa, San Jose, CA (US);
Yanli Zhang, San Jose, CA (US);
Assignee:
SANDISK TECHNOLOGIES INC., Plano, TX (US);
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 27/11 (2006.01); H01L 27/115 (2006.01); H01L 29/788 (2006.01); H01L 29/66 (2006.01); G11C 16/04 (2006.01); H01L 21/764 (2006.01); H01L 29/792 (2006.01);
U.S. Cl.
CPC ...
H01L 27/11551 (2013.01); G11C 16/04 (2013.01); H01L 21/764 (2013.01); H01L 27/11556 (2013.01); H01L 27/11582 (2013.01); H01L 29/66666 (2013.01); H01L 29/66825 (2013.01); H01L 29/66833 (2013.01); H01L 29/788 (2013.01); H01L 29/7889 (2013.01); H01L 29/7926 (2013.01); G11C 16/0483 (2013.01); H01L 27/1157 (2013.01); H01L 27/11519 (2013.01); H01L 27/11524 (2013.01); H01L 27/11565 (2013.01);
Abstract
A NAND device has at least a 3×3 array of vertical NAND strings in which the control gate electrodes are continuous in the array and do not have an air gap or a dielectric filled trench in the array. The NAND device is formed by first forming a lower select gate level having separated lower select gates, then forming plural memory device levels containing a plurality of NAND string portions, and then forming an upper select gate level over the memory device levels having separated upper select gates.