The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 03, 2016

Filed:

Dec. 10, 2013
Applicant:

Infineon Technologies Ag, Neubiberg, DE;

Inventors:

Robert Allinger, Unterhaching, DE;

Gottfried Beer, Nittendorf, DE;

Juergen Hoegerl, Regensburg, DE;

Assignee:

INFINEON TECHNOLOGIES AG, Neubiberg, DE;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 29/10 (2006.01); H01L 23/58 (2006.01); H01L 25/18 (2006.01); H01L 21/66 (2006.01); H01L 23/00 (2006.01); G01R 31/28 (2006.01); H01L 27/02 (2006.01);
U.S. Cl.
CPC ...
H01L 25/18 (2013.01); G01R 31/2884 (2013.01); H01L 22/26 (2013.01); H01L 22/34 (2013.01); H01L 24/09 (2013.01); H01L 27/0248 (2013.01); H01L 2224/0401 (2013.01); H01L 2224/05022 (2013.01); H01L 2224/06131 (2013.01); H01L 2224/06136 (2013.01); H01L 2924/14 (2013.01); H01L 2924/1426 (2013.01); H01L 2924/1434 (2013.01); H01L 2924/14252 (2013.01); H01L 2924/14253 (2013.01);
Abstract

In various embodiments, a chip for a chip package is provided. The chip may include a substrate and an integrated circuit over the substrate. The integrated circuit may include a test circuit, for example a built-in self-test circuit, and an operation circuit, the test circuit including one or more first driver stages each having a first driver performance and the operation circuit including one or more second driver stages each having a second driver performance which is different from the first driver performance, first contacts electrically coupled with the first driver stages, and second contacts electrically coupled with the second driver stages, wherein the test circuit and the first contacts are configured to provide a test mode for testing the integrated circuit and wherein the operation circuit and the second contacts are configured to provide an operating mode of the integrated circuit being different from the test mode.


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