The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
May. 03, 2016
Filed:
Dec. 30, 2010
David White, San Jose, CA (US);
Michael Mcsherry, Portland, OR (US);
Ed Fischer, Salem, OR (US);
Bruce Yanagida, Snohomish, WA (US);
Prakash Gopalakrishnan, Wayne, NJ (US);
David White, San Jose, CA (US);
Michael McSherry, Portland, OR (US);
Ed Fischer, Salem, OR (US);
Bruce Yanagida, Snohomish, WA (US);
Prakash Gopalakrishnan, Wayne, NJ (US);
Cadence Design Systems, Inc., San Jose, CA (US);
Abstract
Disclosed are methods, systems, and articles of manufacture for implementing electronic circuit designs with electro-migration awareness. Some embodiments perform schematic level simulation(s) to determine electrical characteristics, identifies physical parasitics of a layout component, determines the electrical or physical characteristics associated to electro-migration analysis on the component, and determines whether the component meets EM related constraint(s) while implementing the physical design of the electronic circuit in some embodiments. Some embodiments further determine adjustment(s) to the component or related data where the EM related constraints are not met and/or and present the adjustment(s) in the form of hints. Various data and information, such as currents in various forms or voltages, are passed between various schematic level tools and physical level tools.