The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
May. 03, 2016
Filed:
Dec. 28, 2011
Applicants:
Jaydeep P. Kulkarni, Hillsboro, OR (US);
Keith A. Bowman, Hillsboro, OR (US);
James W. Tschanz, Portland, OR (US);
Vivek K. DE, Beaverton, OR (US);
Inventors:
Jaydeep P. Kulkarni, Hillsboro, OR (US);
Keith A. Bowman, Hillsboro, OR (US);
James W. Tschanz, Portland, OR (US);
Vivek K. De, Beaverton, OR (US);
Assignee:
INTEL CORPORATION, Santa Clara, CA (US);
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 11/00 (2006.01); G06F 11/07 (2006.01); G06F 11/10 (2006.01); G11C 29/42 (2006.01); G06F 9/30 (2006.01); G11C 7/18 (2006.01);
U.S. Cl.
CPC ...
G06F 11/0751 (2013.01); G06F 11/1008 (2013.01); G06F 9/30141 (2013.01); G11C 7/18 (2013.01); G11C 29/42 (2013.01);
Abstract
The disclosed system and method detect and correct register file read path errors that may occur as a result of reducing or eliminating supply voltage guardbands and/or frequency guardbands for a CPU, thereby increasing overall energy efficiency of the system.
Quick Actions:
Kulkarni, Jaydeep. (2016). Resilient register file circuit for dynamic variation tolerance and method of operating the same (U.S. Patent No. 9329918). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/9329918
Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile