The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
May. 03, 2016
Filed:
Mar. 12, 2014
Applicant:
Synopsys, Inc., Mountain View, CA (US);
Inventors:
Parthajit Bhattacharya, Bangalore, IN;
Rohit Kapur, Cupertino, CA (US);
Assignee:
Synopsys, Inc., Mountain View, CA (US);
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G01R 31/28 (2006.01); G01R 31/3185 (2006.01); G01R 31/3183 (2006.01); G01R 31/3181 (2006.01); G01R 31/319 (2006.01);
U.S. Cl.
CPC ...
G01R 31/318569 (2013.01); G01R 31/31813 (2013.01); G01R 31/31921 (2013.01); G01R 31/318371 (2013.01); G01R 31/318544 (2013.01);
Abstract
A method for localizing at least one scan flop associated with a fault in an integrated circuit. A first test pattern, including a first scan-in data and first control data, is generated. Based on the first control data of the first test pattern, a first fault data is generated by applying the first scan-in data of the first test pattern to scan flops in a test circuit of the integrated circuit. If the first fault data indicates that a fault may be present in the integrated circuit, a second test pattern, including a second scan-in data and a second control data is generated.