The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 26, 2016

Filed:

Mar. 20, 2014
Applicant:

Stmicroelectronics International N.v., Amsterdam, NL;

Inventors:

Anurag Tiwari, Noida, IN;

Kallol Chatterjee, Kolkata, IN;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H03D 3/24 (2006.01); H04L 7/027 (2006.01); H03L 7/087 (2006.01); H04L 7/033 (2006.01);
U.S. Cl.
CPC ...
H04L 7/027 (2013.01); H03L 7/087 (2013.01); H04L 7/0331 (2013.01); H04L 7/0332 (2013.01);
Abstract

A circuit and method for referenceless CDR with improved efficiency and jitter tolerance by using an additional loop for frequency detection. Such an improved circuit includes a frequency detector for identifying whether an initial recovered clock signal is faster or slower than the actual bit rate of the received data stream. The frequency detector provides a jitter tolerance of +/−0.5 UI and uses significantly fewer components that other conventional frequency detectors. Having fewer components, significantly less power is also consumed. In an embodiment, the FD uses only four flip-flops, two AND gates, and one delay circuit. Having fewer components also uses less die space in integrated circuits. Having high jitter tolerance and fewer components is an improvement over conventional referenceless CDR circuits.


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