The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 26, 2016

Filed:

Sep. 09, 2014
Applicant:

Globalfoundries Inc., Grand Cayman, KY;

Inventors:

Min Gyu Sung, Latham, NY (US);

Kwan-Yong Lim, Niskayuna, NY (US);

Sukwon Hong, Loudonville, NY (US);

Assignee:

GLOBALFOUNDRIES INC., Grand Cayman, KY;

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
H01L 29/78 (2006.01); H01L 21/336 (2006.01); H01L 29/10 (2006.01); H01L 29/66 (2006.01); H01L 21/762 (2006.01); H01L 29/36 (2006.01); H01L 27/092 (2006.01); H01L 21/8238 (2006.01); H01L 29/06 (2006.01);
U.S. Cl.
CPC ...
H01L 29/1033 (2013.01); H01L 21/76224 (2013.01); H01L 21/823807 (2013.01); H01L 21/823821 (2013.01); H01L 27/0924 (2013.01); H01L 29/0649 (2013.01); H01L 29/36 (2013.01); H01L 29/66795 (2013.01); H01L 29/7851 (2013.01);
Abstract

Methods of fabricating circuit structures including FinFET structures are provided, including: providing a substrate and a first material having a first threshold voltage above the substrate, and a second material having a second threshold voltage lower than the first threshold voltage above the first material; forming fins having base fin portions formed from the first material and upper fin portions formed from the second material; providing gate structures over the fins to form one or more FinFET structures, wherein the gate structures wrap around at least the upper fin portions and have an operating voltage lower than the first threshold voltage and higher than the second threshold voltage, so that the upper fin portions define a channel size of the one or more FinFET structures. Circuit structures including FinFET structures are also provided, in which the FinFET structures have a uniform channel size defined only by upper fin portions thereof.


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