The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 26, 2016

Filed:

Jul. 02, 2015
Applicant:

Via Technologies, Inc., New Taipei, TW;

Inventors:

Chen-Yueh Kung, New Taipei, TW;

Wen-Yuan Chang, New Taipei, TW;

Assignee:

VIA Technologies, Inc., New Taipei, TW;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/56 (2006.01); H01L 21/48 (2006.01); H01L 23/48 (2006.01); H01L 21/32 (2006.01); H01L 21/683 (2006.01); H01L 23/00 (2006.01); H01L 23/498 (2006.01); H05K 1/11 (2006.01); H05K 3/24 (2006.01); H05K 3/40 (2006.01); H05K 3/42 (2006.01); H05K 3/46 (2006.01);
U.S. Cl.
CPC ...
H01L 21/4857 (2013.01); H01L 21/32 (2013.01); H01L 21/486 (2013.01); H01L 21/6835 (2013.01); H01L 23/48 (2013.01); H01L 23/49822 (2013.01); H01L 24/81 (2013.01); H05K 1/113 (2013.01); H05K 3/243 (2013.01); H05K 3/4007 (2013.01); H05K 3/423 (2013.01); H05K 3/429 (2013.01); H01L 2221/68345 (2013.01); H01L 2221/68359 (2013.01); H01L 2221/68381 (2013.01); H01L 2224/16238 (2013.01); H01L 2224/8148 (2013.01); H01L 2224/81385 (2013.01); H01L 2224/81395 (2013.01); H01L 2224/81411 (2013.01); H01L 2224/81418 (2013.01); H01L 2224/81423 (2013.01); H01L 2224/81439 (2013.01); H01L 2224/81444 (2013.01); H01L 2224/81449 (2013.01); H01L 2224/81455 (2013.01); H01L 2224/81464 (2013.01); H01L 2224/81469 (2013.01); H01L 2924/12042 (2013.01); H01L 2924/381 (2013.01); H05K 3/4682 (2013.01); H05K 2201/096 (2013.01); H05K 2201/09518 (2013.01); H05K 2201/09563 (2013.01); H05K 2203/016 (2013.01); H05K 2203/1461 (2013.01);
Abstract

A process for fabricating a circuit substrate is provided. The process includes the following steps. A carrier is provided. A conductive layer and a dielectric layer are placed on the carrier, and the conductive layer is located between the carrier and the dielectric layer. The dielectric layer is patterned to form a patterned-dielectric layer having first openings partially exposing the conductive layer. Arc-shaped grooves are formed on the exposed part of the conductive layer. A first-patterned-photoresist layer having second openings respectively connecting the first openings is formed. Conductive structures are formed, wherein each of the conductive structures is integrally formed and includes a pad part, a connection part, and a protruding part; the second openings, the first openings and the arc-shaped grooves are respectively filled with the pad parts, the connection parts and the protruding parts. The first patterned photoresist layer, the carrier and the conductive layer are removed.


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