The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 26, 2016

Filed:

Jan. 27, 2015
Applicant:

Ememory Technology Inc., Hsinchu, TW;

Inventors:

Meng-Yi Wu, Hsinchu County, TW;

Hsin-Ming Chen, Hsinchu, TW;

Chun-Hung Lu, Hsinchu, TW;

Assignee:
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G11C 17/16 (2006.01); G11C 5/06 (2006.01); G11C 16/04 (2006.01); G11C 17/18 (2006.01); H01L 27/112 (2006.01); H01L 29/423 (2006.01); H01L 29/78 (2006.01); H01L 27/115 (2006.01); H01L 29/51 (2006.01); H01L 23/525 (2006.01); H01L 29/93 (2006.01);
U.S. Cl.
CPC ...
G11C 5/06 (2013.01); G11C 16/0408 (2013.01); G11C 17/16 (2013.01); G11C 17/18 (2013.01); H01L 27/11206 (2013.01); H01L 27/11529 (2013.01); H01L 27/11573 (2013.01); H01L 29/42368 (2013.01); H01L 29/512 (2013.01); H01L 29/7817 (2013.01); H01L 29/7835 (2013.01); H01L 23/5252 (2013.01); H01L 29/93 (2013.01);
Abstract

An OTP memory cell including an antifuse unit and a select transistor is provided. The antifuse unit includes an antifuse layer and an antifuse gate disposed on a substrate in sequence, a modified extension doped region disposed in the substrate below the antifuse layer, and a first doped region and a second doped region disposed in the substrate at two opposite sides of the antifuse gate. The select transistor includes a select gate, a gate dielectric layer, a second doped region, and a third doped region. The select gate is disposed on the substrate. The gate dielectric layer is disposed between the select gate and the substrate. The second and the third doped region are respectively disposed in the substrate at two opposite sides of the select gate. The doped region, the antifuse layer and the antifuse gate form a varactor.


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