The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 9323881 B1

PDF
Full Text
Expired
Date of Patent:
Apr. 26, 2016

Filed:

Jul. 25, 2014
Applicants:

Hsiang-jen Tseng, Hsinchu, TW;

Ting-wei Chiang, New Taipei, TW;

Wei-yu Chen, Hsinchu, TW;

Ruei-wun Sun, Shuishang Township, TW;

Hung-jung Tseng, Zhubei, TW;

Shun LI Chen, Tainan, TW;

Li-chun Tien, Tainan, TW;

Inventors:

Hsiang-Jen Tseng, Hsinchu, TW;

Ting-Wei Chiang, New Taipei, TW;

Wei-Yu Chen, Hsinchu, TW;

Ruei-Wun Sun, Shuishang Township, TW;

Hung-Jung Tseng, Zhubei, TW;

Shun Li Chen, Tainan, TW;

Li-Chun Tien, Tainan, TW;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 17/50 (2006.01); H01L 23/482 (2006.01);
U.S. Cl.
CPC ...
G06F 17/5077 (2013.01); G06F 17/5068 (2013.01); G06F 17/5072 (2013.01); H01L 23/4824 (2013.01); H01L 2924/0002 (2013.01);
Abstract

An integrated circuit layout includes a P-type active region and an N-type active region, and a plurality of trunks. The integrated circuit layout further includes a first metal connection connected to the P-type active region; and a second metal connection connected to the N-type active region. Each trunk of the plurality of trunks is electrically connected with the first metal connection and the second metal connection. Each trunk of the plurality of trunks is substantially perpendicular to the first metal connection and the second metal connection. A first trunk of the plurality of trunks has a width wider than a width of other trunks of the plurality of trunks.


Find Patent Forward Citations

Tseng, Hsiang-Jen. (2016). Method and layout of an integrated circuit (U.S. Patent No. 9323881). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/9323881

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

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