The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 19, 2016

Filed:

Oct. 01, 2010
Applicants:

Yoshio Imamura, Ayase, JP;

Tohru Matsumoto, Ayase, JP;

Ryoichi Shimizu, Ayase, JP;

Inventors:

Yoshio Imamura, Ayase, JP;

Tohru Matsumoto, Ayase, JP;

Ryoichi Shimizu, Ayase, JP;

Assignee:

MEIKO ELECTRONICS CO., LTD., Ayase-Shi, Kanagawa, JP;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H05K 13/00 (2006.01); H05K 1/02 (2006.01); H05K 1/18 (2006.01); H05K 1/16 (2006.01);
U.S. Cl.
CPC ...
H05K 13/0023 (2013.01); H05K 1/0269 (2013.01); H05K 1/16 (2013.01); H05K 1/188 (2013.01); H05K 2201/09781 (2013.01); H05K 2201/09918 (2013.01);
Abstract

A thin conductive layer which is to form a conductor pattern () is prepared, a mask layer () is formed on the conductive layer except a plurality of actual connection spots and at least one dummy connection spot on the conductive layer, actual solder pads () and a dummy solder pad () are formed, with use of solder, on the actual connection spots and the dummy connection spot, respectively, where the conductive layer is exposed, connection terminals () of an electric or electronic component () are connected to the actual solder pads (), an insulating base () of resin is formed which is laminated directly on or indirectly via the mask layer () on the conductive layer and in which the component () is embedded, and part of the conductive layer is removed by using the dummy solder pad () as a reference, to form the conductor pattern ().


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