The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 19, 2016

Filed:

Aug. 26, 2013
Applicant:

Cypress Semiconductor Corporation, San Jose, CA (US);

Inventors:

John Cronin, Jericho, VT (US);

Shan Sun, Monument, CO (US);

Thomas Davenport, Denver, CO (US);

Assignee:
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 21/00 (2006.01); H01L 43/02 (2006.01); H01L 27/115 (2006.01); H01L 27/22 (2006.01);
U.S. Cl.
CPC ...
H01L 43/02 (2013.01); H01L 27/11504 (2013.01); H01L 27/11507 (2013.01); H01L 27/228 (2013.01);
Abstract

A method for a non-volatile, ferroelectric random access memory (F-RAM) device that includes a ferroelectric capacitor aligned with a preexisting structure is described. In one embodiment, the method includes forming an opening in an insulating layer over a contact in a planar surface of a substrate to expose at least a portion of the contact. Next a self-aligned contact (SAC) is formed electrically coupling to the contact, the SAC medially located in the opening and proximal to a sidewall thereof. A ferroelectric spacer is then formed in the opening medially of the SAC, and a top electrode spacer formed in the opening over the insulating cap and medially of the ferroelectric spacer.


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