IDiyas

For the Inventor, By the Inventor

The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 9318603 B1

PDFFull Text
Date of Patent:
Apr. 19, 2016

Filed:

Mar. 08, 2014

Method of making a low-rdson vertical power mosfet device

Applicant:

Alpha and Omega Semiconductor Incorporated, Sunnyvale, CA (US);

Inventors:

Yi Su, Cupertino, CA (US);

Daniel Ng, Campbell, CA (US);

Anup Bhalla, Santa Clara, CA (US);

Jun Lu, San Jose, CA (US);

Assignee:

Alpha and Omega Semiconductor Incorporated, Sunnyvale, CA (US);

Attorney:
Primary Examiner:

Laura Menz

Int. Cl.
CPC ...
H01L 21/00 (2006.01); H01L 29/78 (2006.01); H01L 29/417 (2006.01); H01L 29/66 (2006.01); H01L 23/495 (2006.01); H01L 21/306 (2006.01); H01L 29/45 (2006.01); H01L 29/06 (2006.01); H01L 23/00 (2006.01);
U.S. Cl.
CPC ...
H01L 29/7827 (2013.01); H01L 21/30604 (2013.01); H01L 21/30608 (2013.01); H01L 23/495 (2013.01); H01L 23/49503 (2013.01); H01L 23/49513 (2013.01); H01L 23/49562 (2013.01); H01L 24/83 (2013.01); H01L 29/0657 (2013.01); H01L 29/41741 (2013.01); H01L 29/41766 (2013.01); H01L 29/66666 (2013.01); H01L 29/66727 (2013.01); H01L 29/66734 (2013.01); H01L 29/7802 (2013.01); H01L 29/7811 (2013.01); H01L 29/7813 (2013.01); H01L 24/29 (2013.01); H01L 29/0619 (2013.01); H01L 29/0638 (2013.01); H01L 29/456 (2013.01); H01L 2224/291 (2013.01); H01L 2224/293 (2013.01); H01L 2224/2929 (2013.01); H01L 2224/32245 (2013.01); H01L 2224/8309 (2013.01); H01L 2224/83141 (2013.01); H01L 2224/83365 (2013.01); H01L 2224/83385 (2013.01); H01L 2224/83801 (2013.01); H01L 2224/83851 (2013.01); H01L 2924/12036 (2013.01); H01L 2924/12042 (2013.01); H01L 2924/13091 (2013.01);
Abstract

The invention relates to a power semiconductor device and its preparation methods thereof. Particularly, the invention aims at providing a method for reducing substrate contribution to the Rdson (drain-source on resistance) of power MOSFETs, and a power MOSFET device made by the method. By forming one or more bottom grooves at the bottom of Si substrate, the on resistance of the power MOSFET device attributed to the substrate is effectively reduced. A matching lead frame base complementary to the substrate with bottom grooves further improves the package of the power MOSFET device.

Find Patent Forward Citations

Loading…