The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 19, 2016

Filed:

Aug. 22, 2013
Applicant:

Samsung Electronics Co., Ltd., Suwon-Si, Gyeonggi-Do, KR;

Inventors:

Chang-Wook Moon, Seoul, KR;

Joong S. Jeon, Seongnam-si, KR;

Jung-hyun Lee, Yongin-si, KR;

Nae-In Lee, Seoul, KR;

Yeon-Sik Park, Suwon-si, KR;

Hwa-Sung Rhee, Seongnam-si, KR;

Ho Lee, Cheonan-si, KR;

Se-Young Cho, Seoul, KR;

Suk-Pil Kim, Yongin-si, KR;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/02 (2006.01); H01L 29/66 (2006.01); B82Y 10/00 (2011.01); H01L 29/10 (2006.01); H01L 29/78 (2006.01); H01L 29/786 (2006.01); H01L 51/42 (2006.01); H01L 29/06 (2006.01); B82Y 15/00 (2011.01);
U.S. Cl.
CPC ...
H01L 29/66439 (2013.01); B82Y 10/00 (2013.01); H01L 21/02356 (2013.01); H01L 21/02601 (2013.01); H01L 29/0665 (2013.01); H01L 29/0673 (2013.01); H01L 29/1033 (2013.01); H01L 29/66742 (2013.01); H01L 29/7839 (2013.01); H01L 29/78684 (2013.01); B82Y 15/00 (2013.01); H01L 29/0669 (2013.01); H01L 51/426 (2013.01); H01L 2221/1094 (2013.01);
Abstract

A field effect transistor having at least one Ge nanorod and a method of manufacturing the field effect transistor are provided. The field effect transistor may include a gate insulation layer formed on a silicon substrate, at least one nanorod embedded in the gate insulation layer having both ends thereof exposed, a source electrode and a drain electrode connected to opposite sides of the at least one Ge nanorod, and a gate electrode formed on the gate insulation layer between the source electrode and the drain electrode.


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