The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Apr. 19, 2016
Filed:
Sep. 19, 2014
Applicants:
Asanga H. Perera, Austin, TX (US);
Sung-taeg Kang, Austin, TX (US);
Inventors:
Asanga H. Perera, Austin, TX (US);
Sung-Taeg Kang, Austin, TX (US);
Assignee:
FREESCALE SEMICONDUCTOR, INC., Austin, TX (US);
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 29/76 (2006.01); H01L 29/423 (2006.01); H01L 27/115 (2006.01); H01L 21/3213 (2006.01); H01L 21/321 (2006.01); H01L 29/40 (2006.01); H01L 29/66 (2006.01);
U.S. Cl.
CPC ...
H01L 29/42348 (2013.01); H01L 21/3212 (2013.01); H01L 21/32134 (2013.01); H01L 21/32139 (2013.01); H01L 27/1157 (2013.01); H01L 27/11573 (2013.01); H01L 29/401 (2013.01); H01L 29/42372 (2013.01); H01L 29/665 (2013.01);
Abstract
A method of making a semiconductor device includes forming a memory gate structure in a nonvolatile memory region of the semiconductor device, wherein the memory gate structure comprises a first gate separated from a second gate by a charge storage layer. A logic gate structure is formed in a logic region of the semiconductor device. A hard mask is formed over at least the metal electrode portion. The nonvolatile memory region is selectively etched such that a first recess is formed in the first gate and a second recess is formed in the second gate.