The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Apr. 19, 2016
Filed:
Jul. 09, 2012
Applicants:
Toshiyuki Mine, Tokyo, JP;
Yasuhiro Shimamoto, Tokyo, JP;
Hirotaka Hamamura, Tokyo, JP;
Inventors:
Assignee:
Hitachi, Ltd., Tokyo, JP;
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 29/16 (2006.01); H01L 29/66 (2006.01); H01L 29/78 (2006.01); H01L 29/792 (2006.01); H01L 29/06 (2006.01); H01L 29/12 (2006.01); H01L 29/10 (2006.01); H01L 29/423 (2006.01); H01L 29/51 (2006.01);
U.S. Cl.
CPC ...
H01L 29/1608 (2013.01); H01L 29/0657 (2013.01); H01L 29/1079 (2013.01); H01L 29/12 (2013.01); H01L 29/4236 (2013.01); H01L 29/512 (2013.01); H01L 29/517 (2013.01); H01L 29/518 (2013.01); H01L 29/66068 (2013.01); H01L 29/78 (2013.01); H01L 29/7802 (2013.01); H01L 29/7813 (2013.01); H01L 29/7926 (2013.01);
Abstract
The present invention is to cause high channel mobility and a high threshold voltage to coexist in a SiC-MOSFET power device which uses a SiC substrate. The SiC MOSFET which is provided with a layered insulation film having electric charge trap characteristics on a gate insulation film has an irregular threshold voltage in a channel length direction of the SiC MOSFET, and in particular, has a shorter area having a maximum threshold voltage in the channel length direction compared to an area having other threshold voltages.