Semiconductor wafers employing a fixed-coordinate metrology scheme and methods for fabricating integrated circuits using the same

Abstract

Semiconductor wafers employing a fixed coordinate metrology scheme and methods for fabricating integrated circuits using the same are disclosed. In an exemplary embodiment, a semiconductor wafer employing a fixed-coordinate metrology scheme includes an external scribe region in the form of a first rectangular ring, the first rectangular ring defining a first interior space inward from the external scribe region and an interior scribe region in the form of a second rectangular ring, disposed within the first interior space and immediately adjacent to the external scribe region at all points along its exterior perimeter, the second rectangular ring defining a second interior space inward from the interior scribe region, the second interior space being wholly within the first interior space. The semiconductor wafer further includes a technology-specific tile region disposed within the second interior space and immediately adjacent to the interior scribe region and an electrical testable scribe line measurement (ETSLM) region disposed within the second interior space and immediately adjacent to both the technology-specific tile region and the interior scribe region. Still further, the semiconductor wafer includes a free floorplan area disposed within the second interior space and immediately adjacent to both the ETSLM region and the interior scribe region.