The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 19, 2016

Filed:

Apr. 22, 2015
Applicant:

Powerchip Technology Corporation, Hsinchu, TW;

Inventors:

Ming-Chen Lu, Hsinchu, TW;

Chia-Ming Wu, Taipei, TW;

Assignee:

Powerchip Technology Corporation, Hsinchu Science Park, Hsinchu, TW;

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
H01L 27/115 (2006.01); H01L 21/66 (2006.01); H01L 29/66 (2006.01); H01L 29/06 (2006.01); H01L 21/311 (2006.01);
U.S. Cl.
CPC ...
H01L 22/20 (2013.01); H01L 21/31111 (2013.01); H01L 21/31144 (2013.01); H01L 29/0653 (2013.01); H01L 29/66795 (2013.01); H01L 29/66825 (2013.01);
Abstract

A method of fabricating a flash memory includes providing a fin structure. The fin structure includes a floating gate material, an oxide layer and a semiconductive layer. An insulating layer is disposed at two sides of the fin structure. Then, a dielectric layer conformally covers the floating gate material and insulating layer. Later, a patterned first mask layer, a patterned second mask layer, and a control gate are stacked on the dielectric layer from bottom to top. The control gate crosses at least one fin structure. Next, at least one isotropic etching step is performed to entirely remove the exposed dielectric layer.


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