The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 19, 2016

Filed:

Sep. 07, 2012
Applicants:

Tomoaki Atsumi, Kanagawa, JP;

Takashi Okuda, Tokyo, JP;

Inventors:

Tomoaki Atsumi, Kanagawa, JP;

Takashi Okuda, Tokyo, JP;

Assignee:

Semiconductor Energy Laboratory Co., Ltd., Atsugi-shi, Kanagawa-ken, JP;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 21/768 (2006.01); H01L 27/06 (2006.01); H01L 27/108 (2006.01); H01L 27/12 (2006.01); H01L 27/115 (2006.01);
U.S. Cl.
CPC ...
H01L 21/76801 (2013.01); H01L 21/76826 (2013.01); H01L 27/0688 (2013.01); H01L 27/1085 (2013.01); H01L 27/10805 (2013.01); H01L 27/10873 (2013.01); H01L 27/1225 (2013.01); H01L 27/1156 (2013.01);
Abstract

Probability of malfunction of a semiconductor storage device is reduced. A shielding layer is provided between a memory cell array (e.g., a memory cell array including a transistor formed using an oxide semiconductor material) and a peripheral circuit (e.g., a peripheral circuit including a transistor formed using a semiconductor substrate), which are stacked. With this structure, the memory cell array and the peripheral circuit can be shielded from radiation noise generated between the memory cell array and the peripheral circuit. Thus, probability of malfunction of the semiconductor storage device can be reduced.


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