The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 19, 2016

Filed:

Feb. 10, 2014
Applicant:

Globalfoundries Inc., Grand Cayman, KY;

Inventors:

Johannes Mueller, Dresden, DE;

Dina H. Triyoso, Dresden, DE;

Mark Gerard Nolan, Radebeul, DE;

Wenke Weinreich, Dresden, DE;

Konrad Seidel, Dresden, DE;

Patrick Polakowski, Dresden, DE;

Assignee:

GLOBALFOUNDRIES Inc., Grand Cayman, KY;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/02 (2006.01); H01L 21/28 (2006.01); H01L 29/66 (2006.01); H01L 29/94 (2006.01);
U.S. Cl.
CPC ...
H01L 21/02107 (2013.01); H01L 21/0228 (2013.01); H01L 21/02181 (2013.01); H01L 21/02189 (2013.01); H01L 21/02194 (2013.01); H01L 21/28194 (2013.01); H01L 29/66181 (2013.01); H01L 29/94 (2013.01);
Abstract

The present disclosure provides integrated circuit elements and MIM/MIS capacitors having high capacitance and methods of forming according integrated circuit elements and integrated MIM/MIS capacitors and methods of controlling an integrated circuit element and an integrated MIM/MIS capacitor. In various aspects, a substrate is provided and a dielectric layer or insulating layer is formed over the substrate. Furthermore, an electrode layer is disposed over the dielectric layer or insulating layer. Herein, the dielectric layer or insulating layer is in an antiferroelectric phase. In various illustrative embodiments, the integrated circuit element may implement a MOSFET structure or a capacitor structure.


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