The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 19, 2016

Filed:

Dec. 17, 2014
Applicant:

Yield Microelectronics Corp., Hsinchu County, TW;

Inventors:

Hsin-Chang Lin, Hsinchu County, TW;

Wen-Chien Huang, Hsinchu County, TW;

Ya-Ting Fan, Hsinchu County, TW;

Yang-Sen Yeh, Hsinchu County, TW;

Cheng-Ying Wu, Hsinchu County, TW;

Assignee:
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G11C 16/14 (2006.01);
U.S. Cl.
CPC ...
G11C 16/14 (2013.01);
Abstract

A method for operating a small-area EEPROM array is disclosed. The small-area EEPROM array comprises bit lines, word lines, common source lines, and sub-memory arrays. The bit lines are divided into bit line groups. The word lines include a first word line. The common source lines include a first common source line. Each sub-memory array includes a first, second, third and fourth memory cells, which are connected with two bit line groups, a word line and a common source line. The first and second memory cells are symmetric. The third and fourth memory cells are symmetric. The group of the first and second memory cells and the group of the third and fourth memory cells are respectively positioned at two sides of the first common source line. The method operates all operation memory cells and uses special biases to program or erase memory cells massively in a single operation.


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