The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 9312366 B1

PDF
Full Text
Expired
Date of Patent:
Apr. 12, 2016

Filed:

Mar. 23, 2015
Applicant:

International Business Machines Corporation, Armonk, NY (US);

Inventors:

Huihang Dong, Ridgefield, CT (US);

Wai-Kin Li, Hopewell Junction, NY (US);

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/265 (2006.01); H01L 29/66 (2006.01); H01L 29/06 (2006.01); H01L 21/31 (2006.01); H01L 21/3105 (2006.01); H01L 21/3213 (2006.01); H01L 21/283 (2006.01); H01L 21/762 (2006.01); H01L 29/423 (2006.01);
U.S. Cl.
CPC ...
H01L 29/66795 (2013.01); H01L 21/283 (2013.01); H01L 21/31 (2013.01); H01L 21/31056 (2013.01); H01L 21/32135 (2013.01); H01L 21/762 (2013.01); H01L 29/0649 (2013.01); H01L 29/4232 (2013.01);
Abstract

Embodiments of the present disclosure provide a method of processing an integrated circuit (IC) structure for metal gate replacement, the method comprising: providing a structure including a first semiconductor fin and a second semiconductor fin positioned over a buried insulator layer of a silicon-on-insulator (SOI) substrate, and a gate structure positioned over the first and second semiconductor fins, wherein the gate structure includes a gate dielectric layer and a metal layer positioned over the gate dielectric layer; forming a planarizing resist over the first and second semiconductor fins, wherein the planarizing resist includes: a first organic planarizing layer (OPL), and a second OPL over the first OPL; removing a portion of the second OPL; removing an exposed portion of the first OPL and a portion of the metal layer positioned over the second semiconductor fin; and forming a replacement metal gate (RMG) over the gate dielectric layer.


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