The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 12, 2016

Filed:

Dec. 23, 2014
Applicant:

Shanghai Huahong Grace Semiconductor Manufacturing Corporation, Shanghai, CN;

Inventor:

Jian Hu, Shanghai, CN;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 27/11 (2006.01); H01L 21/8244 (2006.01); H01L 21/02 (2006.01); H01L 29/78 (2006.01); G11C 11/412 (2006.01); H01L 27/02 (2006.01);
U.S. Cl.
CPC ...
H01L 27/1104 (2013.01); G11C 11/412 (2013.01); H01L 21/0214 (2013.01); H01L 21/0217 (2013.01); H01L 21/02164 (2013.01); H01L 21/02263 (2013.01); H01L 27/0207 (2013.01); H01L 29/7843 (2013.01);
Abstract

A SRAM cell and a forming method thereof are provided. The SRAM cell includes: a pull-up transistor, a pull-down transistor, a pass gate transistor, a tensile stress film which covers the pull-up transistor and the pull-down transistor, and an interlayer dielectric isolating layer which covers the tensile stress film and the pass gate transistor. The method includes: providing a semiconductor substrate; forming a pull-up transistor, a pull-down transistor and a pass gate transistor on the semiconductor substrate; forming a tensile stress film covering the pull-up and pull-down transistors; and forming an interlayer dielectric isolating layer covering the tensile stress film and the pass gate transistor. Write margin of the SRAM cell may be increased and an area of the SRAM cell may be reduced.


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