The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 12, 2016

Filed:

Apr. 11, 2012
Applicants:

Huaxiang Yin, Beijing, CN;

Xiaolong MA, Beijing, CN;

Qiuxia Xu, Beijing, CN;

Dapeng Chen, Beijing, CN;

Inventors:

Huaxiang Yin, Beijing, CN;

Xiaolong Ma, Beijing, CN;

Qiuxia Xu, Beijing, CN;

Dapeng Chen, Beijing, CN;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 21/8238 (2006.01); H01L 29/78 (2006.01);
U.S. Cl.
CPC ...
H01L 21/823807 (2013.01); H01L 29/7833 (2013.01); H01L 29/7843 (2013.01);
Abstract

The present invention discloses a semiconductor device, comprising a first MOSFET; a second MOSFET; a first stress liner covering the first MOSFET and having a first stress; a second stress liner covering the second MOSFET and having a second stress; wherein the second stress liner and/or the first stress liner comprise(s) a metal oxide. In accordance with the high-stress CMOS and method of manufacturing the same of the present invention, a stress layer comprising a metal oxide is formed selectively on PMOS and NMOS respectively by using a CMOS compatible process, whereby carrier mobility of the channel region is effectively enhanced and the performance of the device is improved.


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