The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 12, 2016

Filed:

Jun. 18, 2015
Applicant:

Taiwan Semiconductor Manufacturing Co., Ltd, Hsin-Chu, TW;

Inventors:

Liang-Chen Chi, Hsinchu, TW;

Chia-Ming Tsai, Hsinchu County, TW;

Chin-Kun Wang, Hsinchu, TW;

Jhih-Jie Huang, Taipei, TW;

Miin-Jang Chen, Taipei, TW;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/8238 (2006.01); H01L 21/28 (2006.01); H01L 29/51 (2006.01);
U.S. Cl.
CPC ...
H01L 21/28229 (2013.01); H01L 21/28185 (2013.01); H01L 21/28202 (2013.01); H01L 29/513 (2013.01); H01L 29/517 (2013.01); H01L 29/518 (2013.01);
Abstract

A method for forming a semiconductor device is provided. The method includes providing a semiconductor substrate. The method includes forming a buffer layer over the semiconductor substrate. The buffer layer is in an amorphous state. The method includes nitriding the buffer layer into a nitride buffer layer. The method includes forming a gate dielectric layer over the nitride buffer layer. The method includes performing a thermal annealing process to convert the gate dielectric layer into a crystalline gate dielectric layer. The method includes forming a gate electrode over the crystalline gate dielectric layer.


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