The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 12, 2016

Filed:

Sep. 30, 2013
Applicant:

Fidelix Co., Ltd., Seongnam-si, Gyeonggi-do, KR;

Inventor:

Seung Han Ahn, Seongnam-si, KR;

Assignee:

FIDELIX CO., LTD., Seongnam-Si, Gyeonggi-Do, KR;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 16/04 (2006.01); G11C 29/00 (2006.01); G11C 16/24 (2006.01); G11C 16/08 (2006.01);
U.S. Cl.
CPC ...
G11C 29/82 (2013.01); G11C 16/24 (2013.01); G11C 16/08 (2013.01);
Abstract

Embodiments of the present invention include a NOR-type flash memory device capable of reducing or eliminating program malfunctions. In some embodiments, the device includes a memory array, row selection circuit, column selection circuit, and program driver circuit. The memory array includes a memory sector having a first sector bit line and a second sector bit line. The memory array also includes a plurality of flash memory cells disposed on a matrix structure having a plurality of cell bit lines and a plurality of word lines arranged sequentially. The cell bit lines are alternately defined as first cell bit lines and second cell bit lines in sequential order. The first cell bit lines are connected to the first sector bit line in response to column selection signals thereof, and the second cell bit lines are connected to the second sector bit line in response to column selection signals thereof.


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