Semiconductor memory device and control method thereof

Abstract

A semiconductor memory device comprises: first lines disposed in a first direction perpendicular to a substrate and extending in a second direction parallel to the substrate; second lines disposed in the second direction and configured to extend in the first direction, the second lines intersecting the first lines; and memory cells disposed at intersections of the first lines and the second lines and each including a variable resistance element. Furthermore, a third line extends in a third direction orthogonal to the first and second directions. A select transistor is connected between the second and third lines. A control circuit controls a voltage applied to the first and third lines, and the select transistor. The control circuit renders conductive at least one of the select transistors and thereby detect a current flowing in the third line, and determines a deterioration state of the select transistor according to a detection result.