The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 12, 2016

Filed:

Jul. 21, 2014
Applicant:

Moon-gyu Jeong, Gwangmyeong-si, KR;

Inventor:

Moon-Gyu Jeong, Gwangmyeong-si, KR;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 17/50 (2006.01); H01L 21/027 (2006.01); G03F 7/20 (2006.01);
U.S. Cl.
CPC ...
G06F 17/5068 (2013.01); H01L 21/027 (2013.01); G03F 7/70466 (2013.01); G06F 17/5081 (2013.01); G06F 2217/12 (2013.01); H01L 21/0274 (2013.01); H01L 2223/54426 (2013.01); Y02P 90/265 (2015.11);
Abstract

Provided are methods of forming patterns of wafers using self-aligned double patterning processes. The methods include preparing an initial layout having a first design pattern, a second design pattern, and a third design pattern disposed between the first design pattern and the second design pattern, extracting a first sub-layout including the first design pattern and a second sub-layout including the second design pattern from the initial layout using a computer, forming a first modified sub-layout including a first modified design pattern obtained by modifying the first design pattern of the first sub-layout using the computer, generating a modified layout including the first modified sub-layout and the second sub-layout using the computer, and performing a double patterning process using the modified layout.


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